Conventionally, in a microprocessor for executing sequentially a plurality of instructions by pipelines, execution of branch instruction is one reason for deteriorating processing efficiency of the processor because it disturbs the pipelines. In order to prevent the processing performance from deteriorating, for example, a technique of using a delay slot is proposed.
A case that a programmer makes the following instruction sequence 1 will be described.
[Instruction Sequence 1]
                (I0) CMPEQ r10, r11        (I1) ADD r1, r2        (I2) BRA F0=1 H′1000        (I3) . . .        (I4) . . .        
An instruction I0 is a comparison instruction for setting a flag F0 if a register 10 and a register 11 are equal as a result of a comparison therebetween. An instruction I1 is an add instruction for writing the addition of a content of register r1 and a content of register r2 in the register r1. An instruction I2 is a conditional branch instruction for branching to an instruction in an address number 1000 of the memory. Instructions I3 and I4 are arbitrary instructions and already input in the microprocessor at a time for executing the instruction I2. When a branch is taken as a result of execution of the instruction I2, the instructions I3 and I4 under the pipeline processing are invalidated.
Accordingly, in consideration of the instruction I1, which is an instruction executed regardless of the branch by the instruction I2 and not an instruction of performing an operation of determining a branch condition of the instruction I2, a scheduling of the instructions as shown in the following instruction sequence 2.
[Instruction Sequence 2]
                (I0) CMPEQ r10, r11        (I2) BRA F0=1H′1000        (I1) ADD r1, r2        (I5) NOP        
Even though a branch to the address number 1000 is determined as a result of the execution of instruction I2, the instruction I1, which is inputted into the pipeline and processed, can further be executed without invalidating the same, wherein in a case of architecture introducing two instructions into the pipeline at the time of executing the instruction I2, a delay slot is occupied by these two instructions. In the case of instruction sequence 2, a delay slot is constituted by the instruction I1 and the instruction I5. The instruction I5 is a so-called no operation (NOP) instruction. After the branch is taken by the instruction I2, an instruction after this branch will be fetched after the instruction I5.
Such a scheduling from the instruction sequence 1 to the instruction sequence 2 is performed by a program itself or a compiler.
Concerning such a scheduling of instructions, various techniques were proposed in “Computer Architecture: A Quantitative Approach, Morgan Kaufmann Co., year 1990”.
Thus, a technology of scheduling instructions in a program was important in order to draw out a processing capability of a microprocessor as much as possible. However, there were various restrictions on the scheduling depending on a type of instruction. In the above case, the conditional branch instruction by the instruction I2 could not be posed before the instruction I0 determining the execution condition of the conditional branch instruction in their instruction sequence. This was because the execution of instruction I0 of determining the branch condition before instruction I2 referred to a content of the flag F0 which was the branch condition by the instruction I2. Thus, not only a conditional branch instruction but also a conditional arithmetic operation instruction, were reasons for deteriorating a degree of freedom in the scheduling of instruction.
In a microprocessor of a type of very long instruction word (VLIW), a plurality of instructions, which could be executed in parallel, were expressed by a single instruction set. In this type, it was necessary to use a high-level scheduling technology considering that which instructions could be executed in parallel, whereby many circumstances that instructions which were meaningless in respect of the program, namely, so-called no operation (NOP) instructions, were inserted in an instruction sequence occurred because of existence of conditional operation instructions. It was also a reason for deteriorating a processing performance of microprocessor to process an no operation (NOP) instruction.